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ltm4619 1 4619fa typical a pplica t ion descrip t ion dual, 26v in , 4a dc/dc module regulator the ltm ? 4619 is a complete dual 4a step-down switch- ing mode dc/dc power supply. included in the package are the switching controller, power fets, inductor, and all support components. operating over input voltage ranges of 4.5v to 26.5v, the ltm4619 supports two outputs with voltage ranges of 0.8v to 5v, each set by a single external resistor. its high efficiency design delivers 4a continuous current (5a peak) for each output. high switching frequency and a current mode architecture enable a very fast transient response to line and load changes without sacrificing stability. the two outputs are interleaved with 180 phase to minimize the ripple noise and reduce the i/o capacitors. the device supports frequency synchronization and output voltage tracking for supply rail sequencing. burst mode operation or pulse- skipping mode can be selected for light load operations. fault protection features include overvoltage protection, overcurrent protection and foldback current limit for short-circuit protection. the low profile package (2.8mm) enables utilization of unused space on the bottom of pc boards for high density point of load regulation. the power module is offered in a space saving and thermally enhanced 15mm 15mm 2.8mm lga package. the ltm4619 is pb-free and rohs compliant. dual 4a 3.3v/2.5v dc/dc module ? regulator fea t ures a pplica t ions n complete standalone power supply n wide input voltage range: 4.5v to 26.5v (ext v cc available for v in 5.5v) n dual 180 out-of-phase outputs with 4a dc typical, 5a peak output current for each n dual outputs with 0.8v to 5v v out range n output voltage tracking n 1.5% maximum total dc output error n current mode control/fast transient response n power good n phase-lockable fixed frequency 250khz to 780khz n on board frequency synchronization n parallel current sharing n selectable burst mode ? operation n output overvoltage protection n small surface mount footprint, low profile (15mm 15mm 2.8mm) lga package n telecom and networking equipment n servers n storage cards n atca cards n industrial equipment n point of load regulation efficiency and power loss at 12v input 4619 ta01a v in v fb1 comp1 v out1 tk/ss1 run1 pgood freq/pllfltr v fb2 comp2 v out2 tk/ss2 run2 extv cc intv cc mode/pllin ltm4619 sgnd pgnd 28k 19.1k 100f 100f v out2 3.3v/4a v out1 2.5v/4a 0.1f 10f 2 0.1f 5.5v to 26.5v 22pf 22pf load current (a) 0 efficiency (%) power loss (w) 95 90 80 70 85 75 60 65 55 2.0 1.5 1.0 0.5 0 3 2 1 1.5 3.5 4619 ta01b 4 2.5 0.5 2.5v out 3.3v out efficiency power loss l , lt, ltc, ltm, linear technology, the linear logo, burst mode and module are registered trademarks and ltpowercad is a trademark of linear technology corporation. all other trademarks are the property of their respective owners.
ltm4619 2 4619fa p in c on f igura t ion a bsolu t e maxi m u m r a t ings v in ............................................................. C0 .3v to 28v intv cc , pgood, run1, run2, extv cc ....... C0.3v to 6v comp1, comp2, v fb1 , v fb2 , ..................... C0 .3v to 2.7v mode/pllin, tk/ss1, tk/ss2, freq/pllfltr ..................................... C0 .3v to intv cc v out1 , v out2 .................................................. 0.8 v to 5v internal operating temperature range (note 2) .................................................. C 40c to 125c maximum reflow body temperature .................... 24 5c storage temperature range .................. C 55c to 125c (note 1) lga package 144-lead (15mm 15mm 2.8mm) top view 1 2 3 4 5 6 7 8 109 11 12 l k j h g f e d c b m a v in sgnd v out1 v out2 gnd run2 extv cc sw2 pgood freq/pllfltr sw1 comp1 comp2 v fb1 v fb2 tk/ss1 tk/ss2 mode/pllin run1 intv cc t jmax = 125c, ja = 13c/w, jp = 6c/w ja derived from 95mm 76mm pcb with 4 layers weight = 1.7g symbol parameter conditions min typ max units v in(dc) input dc voltage v in 5.5v, connect v in and intv cc together l 4.5 26.5 v v out1, 2(range) output voltage range v in = 5.5v to 26.5v l 0.8 5.0 v v out1, 2(dc) output voltage c in = 10f 1, c out = 100f ceramic, 100f poscap, r set = 28.0k? v in = 12v, v out = 2.5v, i out = 0a v in = 12v, v out = 2.5v, i out = 4a l 2.483 2.470 2.52 2.52 2.557 2.570 v v input specifications v in(uvlo) undervoltage lockout thresholds v intvcc rising v intvcc falling 2.00 1.85 2.2 2.0 2.35 2.15 v v o r d er i n f or m a t ion e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at t a = 25c, v in = 12v (note 2). per typical application in figure 18. specified as each channel. (note 3) lead free finish tray part marking* package description temperature range ltm4619ev#pbf ltm4619ev#pbf ltm4619v 144-lead (15mm 15mm 2.8mm) lga C40c to 125c ltm4619iv#pbf ltm4619iv#pbf ltm4619v 144-lead (15mm 15mm 2.8mm) lga C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/
ltm4619 3 4619fa e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at t a = 25c, v in = 12v (note 2). per typical application in figure 18. specified as each channel. (note 3) symbol parameter conditions min typ max units i inrush(vin) input inrush current at start-up i out = 0a, c in = 10f, c out = 100f, v out = 2.5v v in = 12v 0.25 a i q(vin) input supply bias current v in = 12v, v out1 = 2.5v, switching continuous v in = 12v, v out2 = 2.5v, switching continuous v in = 26.5v, v out1 = 2.5v, switching continuous v in = 26.5v, v out2 = 2.5v, switching continuous shutdown, run = 0, v in = 20v 30 30 40 40 40 ma ma ma ma a i s(vin) input supply current v in = 12v, v out = 2.5v, i out = 4a v in = 26.5v, v out = 2.5v, i out = 4a 0.97 0.480 a a intv cc internal v cc voltage v in = 12v, v run > 2v, no load 4.8 5 5.2 v extv cc extv cc switchover voltage extv cc ramping positive l 4.5 4.7 v output specifications i out1, 2(dc) output continuous current range v in = 12v, v out = 2.5v (note 5) 0 4 a v out1(line) v out(nom) line regulation accuracy v out = 2.5v, v in from 6v to 26.5v i out = 0a for each output l 0.15 0.25 0.3 0.5 % % v out2(line) v out(nom) line regulation accuracy v out = 2.5v, v in from 6v to 26.5v i out = 0a for each output l 0.15 0.25 0.3 0.5 % % v out1(load) v out1(nom) load regulation accuracy for each output, v out = 2.5v, 0a to 4a (note 5) v in = 12v l 0.6 0.8 % v out2(load) v out2(nom) load regulation accuracy for each output, v out = 2.5v, 0a to 4a (note 5) v in = 12v l 0.6 0.8 % v out1, 2(ac) output ripple voltage i out = 0a, c out = 100f x5r ceramic v in = 12v, v out = 2.5v v in = 26.5v, v out = 2.5v 20 25 mv mv f s output ripple voltage frequency i out = 2a, v in = 12v, v out = 2.5v freq/pllfltr = intv cc 780 khz v outstart turn-on overshoot c out = 100f x5r ceramic, v out = 2.5v, i out = 0a v in = 12v v in = 26.5v 10 10 mv mv t start turn-on time c out = 100f x5r ceramic, v out = 2.5v, i out = 0a resistive load, v in = 12v v in = 26.5v 0.250 0.130 ms ms v outls peak deviation for dynamic load load: 0% to 50% to 0% of full load c out = 100f x5r ceramic,v out = 2.5v, v in = 12v 15 mv t settle settling time for dynamic load step load: 0% to 50% to 0% of full load c out = 100f x5r ceramic,v out = 2.5v, v in = 12v 10 s i outpk output current limit c out = 100f x5r ceramic, v in = 6v, v out = 2.5v v in = 26.5v, v out = 2.5v 12 11 a a control section v fb1 , v fb2 voltage at v fb pin i out = 0a, v out = 2.5v l 0.792 0.788 0.8 0.8 0.808 0.810 v i tk/ss1, 2 soft-start charge current v tk/ss = 0v, v out = 2.5v 0.9 1.3 1.7 a df max maximum duty factor in dropout (note 4) 97 % t on(min) minimum on-time (note 4) 90 ns
ltm4619 4 4619fa elec t rical charac t eris t ics typical p er f or m ance c harac t eris t ics the l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at t a = 25c, v in = 12v (note 2). per typical application in figure 18. specified as each channel. (note 3) symbol parameter conditions min typ max units f nom nominal frequency v freq = 1.2v 450 500 550 khz f low lowest frequency v freq = 0v 210 250 290 khz f high highest frequency v freq 2.4v 700 780 860 khz r mode/pllin mode/pllin input resistance 250 k i freq frequency setting sinking current sourcing current f mode > f osc f mode < f osc C13 13 a a v run1, 2 run pin on/off threshold run rising run falling 1.1 1.02 1.22 1.14 1.35 1.27 v v r fb1 , r fb2 resistor between v out and v fb pins for each channel 60.1 60.4 60.7 k? v pgl pgood voltage low i pgood = 2ma 0.1 0.3 v i pgood pgood leakage current v pgood = 5v 2 a v pgood pgood range v fb ramping negative v fb ramping positive C5 5 C7.5 7.5 C10 10 % % note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltm4619e is guaranteed to meet performance specifications over the 0c to 125c internal operating temperature range. specifications over the full C40c to 125c internal operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltm4619i is guaranteed to meet specifications over the full internal operating temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. note 3: the two outputs are tested separately and the same testing condition is applied to each output. note 4: 100% tested at wafer level only. note 5: see output current derating curves for different v in , v out and t a . efficiency vs load current with 5v in (f = 500khz for 0.8v out , 1.2v out and 1.5v out ) efficiency vs load current with 12v in (f = 500khz for 1.2v out and 1.5v out ) efficiency vs load current with 24v in (f = 500khz for 1.5v out ) (refer to figures 18 and 19) load current (a) 0 efficiency (%) 95 85 90 75 65 80 70 60 55 2.5 1.5 3.5 4619 g01 4 2 0.5 1 3 0.8v out 1.2v out 1.5v out 2.5v out 3.3v out load current (a) 0 efficiency (%) 95 85 90 75 65 80 70 60 55 2.5 1.5 3.5 4619 g02 4 2 0.5 1 3 5v out 1.2v out 1.5v out 2.5v out 3.3v out load current (a) 0 efficiency (%) 95 85 90 75 65 80 70 60 55 50 45 2.5 1.5 3.5 4619 g03 4 2 0.5 1 3 5v out 1.5v out 2.5v out 3.3v out
ltm4619 5 4619fa typical p er f or m ance c harac t eris t ics 3.3v output transient response start-up, i out = 0a start-up, i out = 4a short circuit, i out = 0a short circuit, i out = 4a 1.2v output transient response 1.5v output transient response 2.5v output transient response (refer to figures 18 and 19) i out 1a/div v out 50mv/div 100s/div 4619 g04 6v in 1.2v out at 2a/s load step f = 780khz c out 2 22f, 6.3v x5r ceramic c out 1 330f, 6.3v sanyo poscap i out 1a/div v out 50mv/div 100s/div 4619 g05 6v in 1.5v out at 2a/s load step f = 780khz c out 2 22f, 6.3v x5r ceramic c out 1 330f, 6.3v sanyo poscap i out 1a/div v out 50mv/div 100s/div 4619 g06 6v in 2.5v out at 2a/s load step f = 780khz c out 2 22f, 6.3v x5r ceramic c out 1 330f, 6.3v sanyo poscap i out 1a/div v out 50mv/div 100s/div 4619 g07 6v in 3.3v out at 2a/s load step f = 780khz c out 2 22f, 6.3v x5r ceramic c out 1 330f, 6.3v sanyo poscap i in 0.5a/div v in 1v/div 20ms/div 4619 g08 v in = 12v, v out = 2.5v, i out = 0a c out = 2 22f 10v and 1 100f 6.3v ceramic caps c softstart = 0.1f use run pin to control start-up i in 0.5a/div v in 1v/div 20ms/div 4619 g09 v in = 12v, v out = 2.5v, i out = 4a resistive load c out = 2 22f 10v, and 1 100f 6.3v ceramic caps c softstart = 0.1f use run pin to control start-up i in 0.5a/div v out 1v/div 50s/div 4619 g10 v in = 12v, v out = 2.5v, i out = 0a c out = 2 22f 10v, and 1 100f 6.3v ceramic caps i in 0.5a/div v out 1v/div 50s/div 4619 g11 v in = 12v, v out = 2.5v, i out = 4a c out = 2 22f 10v, and 1 100f 6.3v ceramic caps
ltm4619 6 4619fa p in func t ions v in (j1 to j3, j10 to j12, k1 to k4, k9 to k12, l1 to l5, l8 to l12, m1 to m12): power input pins. apply input voltage between these pins and pgnd pins. recommend placing input decoupling capacitance directly between v in pins and pgnd pins. for v in < 5.5, tie v in and intv cc together. v out1 , v out2 (a10 to d10, a11 to d11, a12 to d12, a1 to d1, a2 to d2, a3 to d3): power output pins. apply output load between these pins and pgnd pins. recommend placing output decoupling capacitance directly between these pins and pgnd pins. pgnd (h1, h2, h4, h9, h11, h12, g1 to g12, f1 to f5, f7 to f12, e1 to e12, d4 to d9, c4 to c9, b4 to b9, a4 to a9): power ground pins for both input and output returns. intv cc (f6): internal 5v regulator output. this pin is for additional decoupling of the 5v internal regulator. extv cc (j4): external power input to controller. when extv cc is higher than 4.7v, the internal 5v regulator is disabled and external power supplies current to reduce the power dissipation in the module. this will improve the efficiency more at high input voltages. sgnd (j6, j7, h6, h7): signal ground pin. return ground path for all analog and low power circuitry. tie a single connection to pgnd in the application. mode/pllin (h8): mode selection or external synchroniza- tion pin. tying this pin high enables pulse-skipping mode. tying this pin low enables force continuous operation. floating this pin enables burst mode operation. a clock on the pin will force the controller into the continuous mode of operation and synchronize the internal oscillator. the suitable synchronizable frequency range is 250khz to 780khz subject to inductor ripple current limits described in the freq/pllfltr pin section. the external clock input high threshold is 1.6v, while the input low threshold is 1v. freq/pllfltr (j8): frequency selection pin. an internal lowpass filter is tied to this pin. the frequency can be selected from 250khz to 780khz by varying the dc volt - age on this pin from 0v to 2.4v. the nominal frequency setting is 500khz. frequency selection can be modified as long as the inductor ripple current is less 40% to 50% at the output current i ripple = 1 freq 1? v out v in ? ? ? ? ? ? v out l where freq is selected operating frequency and l is the inductor value. leave this pin floating when external synchronization is used. tk/ss1, tk/ss2 (k8, k5): output voltage tracking and soft-start pins. internal soft-start currents of 1.3a charge the soft-start capacitors. see the applications information section to use the tracking function. v fb1 , v fb2 (k7, k6): the negative input of the error amplifier. internally, this pin is connected to v out with a 60.4k precision resistor. different output voltages can be programmed with an additional resistor between v fb and sgnd pins. see the applications information section for details. comp1, comp2 (l7, l6): current control threshold and error amplifier compensation point. the module has been internally compensated for most i/o ranges. pgood (h5): output voltage power good indicator. open drain logic output that is pulled to ground when the output voltage is not within 7.5% of the regulation point. run1, run2 (j9, j5): run control pins. 0.5a pull-up currents on these pins turn on the module if these pins are floating. forcing either of these pins below 1.2v will shut down the corresponding outputs. an additional 4.5a pull-up current is added to this pin, once the run pin rises above 1.2v. also, active control or pull-up resistors can be used to enable the run pin. the maximum voltage is 6v on these pins. sw1, sw2 (h10, h3): switching test pins. these pins are provided externally to check the operation frequency.
ltm4619 7 4619fa s i m pli f ie d b lock diagra m decoupling r equire m en t s 4619 bd intv cc pgood mode/pllin extv cc tk/ss1 run1 comp1 tk/ss2 run2 comp2 freq sgnd m3 m4 internal comp internal filter c ss2 internal filter 10f 1.5f l2 1.5h 60.4k c in + v in 4.5v to 26.5v* c out2 r set2 19.1k + v out2 3.3v/4a v fb2 pgnd m1 m2 c ss1 v in power control 10f l1 1.5h 60.4k c out1 r set1 28k + v out1 2.5v/4a v fb1 pgnd pgnd sw1 sw2 1.5f pgnd internal comp *use extv cc for v in 5.5v, or tie v in and extv cc together for v in 5.5v r1 r2 r2 r1 + r2 ? ? ? ? ? ? ? v in = uvlo threshold = 1.22v symbol parameter conditions min typ max units c in external input capacitor requirement (v in = 4.5v to 26.5v, v out1 = 2.5v, v out2 = 3.3v) i out1 = 4a, i out2 = 4a 10 f c out1 c out2 external output capacitor requirement (v in = 4.5v to 26.5v, v out1 = 2.5v, v out2 = 3.3v) i out1 = 4a i out2 = 4a 200 200 f f t a = 25c. use figure 1 configuration. figure 1. simplified ltm4619 block diagram
ltm4619 8 4619fa o pera t ion the ltm4619 is a dual-output standalone non-isolated switching mode dc/dc power supply. it can deliver up to 4a (dc current) for each output with few external input and output capacitors. this module provides precisely regulated output voltages programmable via external resistors from 0.8vdc to 5.0vdc over 4.5v to 26.5v input voltages. the typical application schematic is shown in figure 18. the ltm4619 has integrated constant frequency current mode regulators and built-in power mosfet devices with fast switching speed. the typical switching frequency is 780khz. to reduce switching noise, the two outputs are interleaved with 180 phase internally and can be syn- chronized externally using the pllin pin. with current mode control and internal feedback loop compensation, the ltm4619 module has sufficient stabil - ity margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. current mode control provides cycle-by-cycle fast current limit and current foldback in a short-circuit condition. internal overvoltage and undervoltage comparators pull the open-drain pgood output low if the output feedback voltage exits a 7.5% window around the regulation point. the power good pin is disabled during start-up. pulling the run pin below 1.2v forces the controller into its shutdown state, by turning off both mosfets. the tk/ss pin is used for programming the output voltage ramp and voltage tracking during start-up. see the ap- plications information section. the ltm4619 is internally compensated to be stable over all operating conditions. ltpowercad? is available for transient and stability analysis. the v fb pin is used to program the output voltage with a single external resistor to ground. multiphase operation can be easily employed with the synchronization. high efficiency at light loads can be accomplished with selectable burst mode operation or pulse-skipping mode using the mode pin. efficiency graphs are provided for light load operations in the typical performance charac - teristics section.
ltm4619 9 4619fa the typical ltm4619 application circuit is shown in figure 18. external component selection is primarily deter - mined by the maximum load current and output voltage. output voltage programming the pwm controller has an internal 0.8v reference voltage. as shown in the block diagram, a 60.4k internal feedback resistor r fb connects v out to v fb pin. the output voltage will default to 0.8v with no feedback resistor. adding a resistor r set from v fb pin to sgnd programs the output voltage: v out = 0.8v ? 60.4k + r set r set or equivalently r set = 60.4k v out 0.8v ? 1 ? ? ? ? ? ? table 1. v fb resistor table vs various output voltages v out (v) 0.8 1.2 1.5 1.8 2.5 3.3 5 r set (k) open 121 68.1 48.7 28.0 19.1 11.5 input capacitors the ltm4619 module should be connected to a low ac- impedance dc source. two 1.5f input ceramic capacitors are included inside the module. additional input capacitors are needed if a large load is required up to the 4a level. a 47f to 100f surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. this bulk capacitor is only needed if the input source im - pedance is compromised by long inductive leads, traces or not enough source capacitance. for a buck converter, the switching duty-cycle can be estimated as: d = v out v in without considering the inductor current ripple, for each output, the rms current of the input capacitor can be estimated as: i cin(rms) = i out(max) ? d ? (1 ? d) in the above equation, is the estimated efficiency of the power module. the bulk capacitor can be a switcher-rated electrolytic aluminum capacitor, polymer capacitor for bulk input capacitance due to high inductance traces or leads. one 10f ceramic input capacitor is typically rated for 2a of rms ripple current, so the rms input current at the worst case for each output at 4a maximum current is about 2a. if a low inductance plane is used to power the device, then two 10f ceramic capacitors are enough for both outputs at 4a load and no external input bulk capacitor is required. output capacitors the ltm4619 is designed for low output voltage ripple noise. the bulk output capacitors defined as c out are chosen with low enough effective series resistance (esr) to meet the output voltage ripple and transient require - ments. c out can be the low esr tantalum capacitor, the low esr polymer capacitor or ceramic capacitor. the typical output capacitance range for each output is from 47f to 220f. additional output filtering may be required by the system designer. if further reduction of output ripples or dynamic transient spikes is required, ltpowercad is available for stability analysis. multiphase operation will reduce effective output ripple as a function of the num - ber of phases. application note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. ltpowercad calculates the output ripple reduction as the number of implemented phases increased by n times. a pplica t ions i n f or m a t ion
ltm4619 10 4619fa mode selections and phase-locked loop the ltm4619 can be enabled to enter high efficiency burst mode operation, constant-frequency pulse-skipping mode, or forced continuous conduction mode. to select the forced continuous operation, tie the mode/pllin pin to a dc voltage below 0.8v. to select pulse-skipping mode of operation, tie the mode/pllin pin to intv cc . to select burst mode operation, float the mode/pllin pin. frequency synchronization a phase-lock loop is available on the ltm4619 to synchro - nize the internal clock to an external clock source connected on the mode/pllin pin. the clock high level needs to be higher than 1.6v and the clock low level needs to be lower than 1v. the frequency programming voltage and or the programming voltage divider must be removed from the freq/pllfltr pin when synchronizing to an external clock. the freq/pllfltr pin has the required onboard pll filter components for clock synchronization. the ltm will default to forced continuous mode while being clock synchronized. channel 1 is synchronized to the rising edge on the external clock, and channel 2 is 180 degrees out-of-phase with the external clock. applica t ions in f or m a t ion frequency selection the switching frequency of the ltm4619s controllers can be selected using the freq/pllfltr pin. if the mode/ pllin pin is not being driven by an external clock source, the freq/pllfltr pin can be set from 0v to 2.4v to pro - gram the controllers operating frequency from 250khz to 780khz using a voltage divider to intv cc (see figure 19). the typical frequency is 780khz. if the output is too low or the minimum on-time is reached, the frequency needs to decrease to enlarge the turn-on time. otherwise, a significant amount of cycle skipping can occur with cor - respondingly larger current and voltage ripple. refer to the figure of output voltage vs minimum on-time to choose a proper frequency. figure 2. switching frequency vs freq/pllfltr pin voltage freq pin voltage (v) 0 frequency (khz) 0.5 1 1.5 2 4619 f02 2.5 0 100 300 400 500 900 800 700 200 600
ltm4619 11 4619fa a pplica t ions i n f or m a t ion figure 3. example of coincident tracking output voltage tracking can be programmed externally using the tk/ss pin. the master channel is divided down with an external resistor divider that is the same as the slave channels feedback divider to implement coincident tracking. the ltm4619 uses an accurate 60.4k resistor internally for the top feedback resistor. figure 3 shows an example of coincident tracking. figure 4 shows the output voltages with coincident tracking. v slave = 1+ r1 r2 ? ? ? ? ? ? ? v track v track is the track ramp applied to the slaves tk/ss2 pin. v track has a control range of 0v to 0.8v. when the masters output is divided down with the same resistor values used to set the slaves output, then the slave will coincident track with the master until it reaches its final value. the master will continue to its final value from the slaves regulation point. ratiometric modes of tracking can be achieved by select- ing different divider resistors values to change the output tracking ratio. the master output must be greater than the slave output for the tracking to work. master and slave data inputs can be used to implement the correct resistors values for coincident or ratiometric tracking. soft-start and tracking the ltm4619 has the ability to either soft-start by itself with a capacitor or track the output of another channel or external supply. when one particular channel is configured to soft-start by itself, a capacitor should be connected to its tk/ss pin. this channel is in the shutdown state if its run pin voltage is below 1.2v. its tk/ss pin is actively pulled to ground in this shutdown state. once the run pin voltage is above 1.2v, the channel pow - ers up. a soft-start current of 1.3a then starts to charge its soft-start capacitor. note that soft-start or tracking is achieved not by limiting the maximum output current of the controller but by controlling the output ramp voltage according to the ramp rate on the tk/ss pin. current foldback is disabled during this phase to ensure smooth soft-start or tracking. the soft-start or tracking range is defined to be the voltage range from 0v to 0.8v on the tk/ss pin. the total soft-start time can be calculated as: t soft-start = 0.8v ? c ss 1.3a figure 4. coincident tracking 4619 f03 v in v fb1 comp1 v out1 tk/ss1 run1 pgood freq/pllfltr v fb2 comp2 v out2 tk/ss2 run2 extv cc intv cc mode/pllin ltm4619 sgnd pgnd r3 19.1k r4 28k c out2 c out1 v out1 3.3v v out2 2.5v c1 0.1f c in v in 5.5v to 28v c2 22pf c3 22pf r1 60.4k r2 28k v out1 time output voltage 4619 f04 master output slave output
ltm4619 12 4619fa applica t ions in f or m a t ion duty factor (v out /v in ) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 4619 f05 rms input ripple current dc load current 6-phase 4-phase 3-phase 2-phase 1-phase duty cycle (v out /v in ) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 1.00 0.95 0.90 0.85 0.80 0.75 0.70 0.65 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 4619 f06 peak-to-peak output ripple current dir ratio = 6-phase 4-phase 3-phase 2-phase 1-phase figure 5. normalized input rms ripple current vs duty factor for one to six phases figure 6. normalized output ripple current vs duty cycle, dlr = v out t/l
ltm4619 13 4619fa multiphase operation multiphase operation with multiple ltm4619 devices in parallel will lower the effective input rms ripple current as well as the output ripple current due to the interleaving operation of the regulators. figure 5 provides a ratio of input rms ripple current to dc load current as a function of duty cycle and the number of paralleled phases. choose the corresponding duty factor and the number of phases to get the correct ripple current value. for example, the 2-phase parallel for one ltm4619 design provides 8a at 2.5v output from a 12v input. the duty cycle is dc = 2.5v/12v = 0.21. the 2-phase curve has a ratio of ~0.25 for a duty cycle of 0.21. this 0.25 ratio of rms ripple cur - rent to a dc load current of 8a equals ~2a of input rms ripple current for the external input capacitors. the effective output ripple current is lowered with mul - tiphase operations as well. figure 6 provides a ratio of peak-to-peak output ripple current to the normalized output ripple current as a function of duty factor and the number of paralleled phases. choose the corresponding duty factor and the number of phases to get the correct output ripple current ratio value. if a 2-phase operation is chosen at 12v in to 2.5v out with a duty factor of 21%, then 0.6 is the ratio of the normalized output ripple current to inductor ripple dir at the zero duty factor. this leads to ~1.3a of the effective output ripple current i l if the dir is at 2.2a. refer to application note 77 for a detailed explanation of the output ripple current reduction as a function of paralleled phases. the output voltage ripple has two components that are related to the amount of bulk capacitance and effective series resistance (esr) of the output bulk capacitance. therefore, the output voltage ripple can be calculated with the known effective output ripple current. the equation: v out(p-p) i l /(8 ? f ? n ? c out ) + esr ? i l where f is frequency and n is the number of parallel phases. a pplica t ions i n f or m a t ion run pin the run pins can be used to enable or sequence the particular regulator channel. the run pins have their own internal 0.5a current source to pull up the pin to 1.2v, and then the current increases to 4.5a above 1.2v. careful consideration is needed to assure that board contamination or residue does not load down the 0.5a pull-up current. otherwise active control to these pins can be used to activate the regulators. a voltage divider can be used from v in to set an enable point that can be used as a uvlo feature for the regulator. the resistor divider needs to be low enough resistance to swamp out the pull- up current sources and not enable the device when not attended. see the simplified block diagram. power good the pgood pin is connected to an open drain of an internal n-channel mosfet. the mosfet turns on and pulls the pgood pin low when either v fb pin voltage is not within 7.5% of the 0.8v reference voltage. the pgood pin is also pulled low when either run pin is below 1.2v or when the ltm4619 is in the soft-start or tracking phase. when the v fb pin voltage is within the 7.5% requirement, the mosfet is turned off and the pin is allowed to be pulled up by an external resistor to a source of up to 6v. the pgood pin will flag power good immediately when both v fb pins are within the 7.5% window. however, there is an internal 17s power bad mask when either v fb goes out of the 7.5% window.
ltm4619 14 4619fa applica t ions in f or m a t ion intv cc and extv cc the intv cc is the internal 5v regulator that powers the ltm4619 internal circuitry and drives the power mosfets. the input voltage of the ltm4619 must be 6v or above for the intv cc to regulate to the proper 5v level due to the internal ldo dropout from the input voltage. for ap- plications that need to operate below 6v input, then the input voltage can be connected directly to the extv cc pin to bypass the ldo dropout concern, or an external 5v supply can be used to power the extv cc pin when the input voltage is at high end of the supply range to reduce power dissipation in the module. for example the dropout voltage for 24v input would be 24v C 5v = 19v. this 19v headroom then multiplied by the power mosfet drive current of ~15ma would equal ~0.3w additional power dissipation. so utilizing an external 5v supply on the extv cc would improve design efficiency and reduce device temperature rise. slope compensation the module has already been internally compensated for all output voltages. ltpowercad is available for control loop optimization. burst mode operation and pulse-skipping mode the ltm4619 regulator can be placed into high efficiency power saving modes at light load condition to conserve power. the burst mode operation can be selected by float - ing the mode/pllin pin, and pulse-skipping mode can be selected by pulling the mode/pllin pin to intv cc . burst mode operation offers the best efficiency at light load, but output ripple will be higher and lower frequency ranges are capable which can interfere with some systems. pulse- skipping mode efficiency is not as good as burst mode operation, but this mode only skips pulses to save efficiency and maintains a lower output ripple and a higher switch- ing frequency. burst mode operation and pulse-skipping mode efficiencies can be reviewed in graph supplied in the typical performance characteristics section. fault conditions: current limit and overcurrent foldback the ltm4619 has a current mode controller, which inher - ently limits the cycle-by-cycle inductor current not only in steady-state operation, but also in transient. to further limit current in the event of an overload condi - tion, the ltm4619 provides foldback current limiting. if the output voltage falls by more than 50%, then the maximum output current is progressively lowered to one-third of its full current limit value. foldback current limiting is disabled during the soft-start and tracking up. thermal considerations and output current derating in different applications, the ltm4619 operates in a variety of thermal environments. the maximum output current is limited by the environmental thermal condition. sufficient cooling should be provided to ensure reliable operation. when the cooling is limited, proper output current derat- ing is necessary, considering the ambient temperature, airflow, input/output conditions, and the need for increased reliability. two outputs of ltm4619 are paralleled to get high output current for derating curve tests. the power loss curves in figures 7 and 8 can be used in coordination with the load current derating curves in figures 9 to 16 for calculating an approximate ja for the module with various cooling methods. application note 103 provides a detailed ex- planation of the analysis for the thermal models and the derating curves. tables 2 and 3 provide a summary of the equivalent ja for the noted conditions. these equivalent ja parameters are correlated to the measured values, and are improved with airflow. the junction temperature is maintained at 125c or below for the derating curves. safety considerations the ltm4619 modules do not provide isolation from v in to v out . there is no internal fuse. if required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure.
ltm4619 15 4619fa applica t ions in f or m a t ion figure 7. power loss at 1.5v output figure 8. power loss at 3.3v output load current (a) 0 power loss (w) 3.0 2.5 1.5 0.5 2.0 1.0 0 6 4 2 4619 f07 8 6v loss 12v loss load current (a) 0 power loss (w) 4.5 2.5 3.0 3.5 4.0 1.5 0.5 2.0 1.0 0 6 4 2 4619 f08 8 12v loss 24v loss table 2. 1.5v output derating curve v in (v) power loss curve airflow (lfm) heatsink ja (c/w) figures 9, 11 6, 12 figure 7 0 none 12.8 figures 9, 11 6, 12 figure 7 200 none 9.0 figures 9, 11 6, 12 figure 7 400 none 8.0 figures 10, 12 6, 12 figure 7 0 bga heatsink 11.9 figures 10, 12 6, 12 figure 7 200 bga heatsink 8.4 figures 10, 12 6, 12 figure 7 400 bga heatsink 7.4 table 3. 3.3v output derating curve v in (v) power loss curve airflow (lfm) heatsink ja (c/w) figures 13, 15 12, 24 figure 8 0 none 13.4 figures 13, 15 12, 24 figure 8 200 none 9.6 figures 13, 15 12, 24 figure 8 400 none 8.5 figures 14, 16 12, 24 figure 8 0 bga heatsink 12.5 figures 14, 16 12, 24 figure 8 200 bga heatsink 8.9 figures 14, 16 12, 24 figure 8 400 bga heatsink 7.9 heatsink manufacturer part number website aavid thermalloy 375424b00034g www.aavid.com
ltm4619 16 4619fa figure 12. 12v in to 1.5v out with heat sink figure 13. 12v in to 3.3v out without heat sink figure 14. 12v in to 3.3v out with heat sink figure 15. 24v in to 3.3v out without heat sink figure 16. 24v in to 3.3v out with heat sink figure 9. 6v in to 1.5v out without heat sink figure 10. 6v in to 1.5v out with heat sink figure 11. 12v in to 1.5v out without heat sink ambient temperature (c) 70 load current (a) 8 4 5 6 7 2 3 1 0 110105 80 85 90 95 100 75 4619 f09 115 6v in to 1.5v out 0lfm 6v in to 1.5v out 200lfm 6v in to 1.5v out 400lfm ambient temperature (c) 70 load current (a) 8 4 5 6 7 2 3 1 0 110105 80 85 90 95 100 75 4619 f10 115 6v in to 1.5v out 0lfm 6v in to 1.5v out 200lfm 6v in to 1.5v out 400lfm ambient temperature (c) 70 load current (a) 8 4 5 6 7 2 3 1 0 110105 80 85 90 95 100 75 4619 f11 115 12v in to 1.5v out 0lfm 12v in to 1.5v out 200lfm 12v in to 1.5v out 400lfm ambient temperature (c) 70 load current (a) 8 4 5 6 7 2 3 1 0 110105 80 85 90 95 100 75 4619 f12 115 12v in to 1.5v out 0lfm 12v in to 1.5v out 200lfm 12v in to 1.5v out 400lfm ambient temperature (c) 60 load current (a) 8 4 5 6 7 2 3 1 0 105100 75 80 85 90 95 7065 4619 f13 110 12v in to 3.3v out 0lfm 12v in to 3.3v out 200lfm 12v in to 3.3v out 400lfm ambient temperature (c) 60 load current (a) 8 4 5 6 7 2 3 1 0 105100 75 80 85 90 95 7065 4619 f14 110 12v in to 3.3v out 0lfm 12v in to 3.3v out 200lfm 12v in to 3.3v out 400lfm ambient temperature (c) 40 load current (a) 8 4 5 6 7 2 3 1 0 100 70 80 90 6050 4619 f15 24v in to 3.3v out 0lfm 24v in to 3.3v out 200lfm 24v in to 3.3v out 400lfm ambient temperature (c) 40 load current (a) 8 4 5 6 7 2 3 1 0 100 70 80 90 6050 4619 f16 24v in to 3.3v out 0lfm 24v in to 3.3v out 200lfm 24v in to 3.3v out 400lfm applica t ions in f or m a t ion
ltm4619 17 4619fa a pplica t ions in f or m a t ion figure 17. recommended pcb layout top view 1 2 3 4 5 6 7 8 109 11 12 l k j h g f e d c b m a pgnd pgnd v in pgnd v out2 v out1 c out1 c out2 c in2 c in1 layout checklist/example the high integration of ltm4619 makes the pcb board layout very simple and easy. however, to optimize its electri - cal and thermal performance, some layout considerations are still necessary. ? use large pcb copper areas for high current path, includ - ing v in , pgnd, v out1 and v out2 . it helps to minimize the pcb conduction loss and thermal stress. ? place high frequency ceramic input and output capaci - tors next to the v in , pgnd and v out pins to minimize high frequency noise. ? place a dedicated power ground layer underneath the unit. ? to minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnections between top layer and other power layers. ? do not put vias directly on the pad. ? use a separated sgnd ground copper area for com - ponents connected to signal pins. connect the sgnd to pgnd underneath the unit. ? decouple the input and output grounds to lower the output ripple noise. refer to figure 17. figure 17 gives a good example of the recommended layout.
ltm4619 18 4619fa figure 18. typical 4.5v to 26.5v input, 5v and 3.3v outputs at 4a design typical a pplica t ions 4619 f18 v in v fb1 comp1 v out1 tk/ss1 run1 pgood freq/pllfltr v fb2 comp2 v out2 tk/ss2 run2 extv cc intv cc mode/pllin ltm4619 sgnd pgnd 11.5k 100k r1 (opt*) 19.1k c out2 100f c out1 100f v out2 3.3v/4a v out1 5v/4a 0.1f c in 10f 2 0.1f v in 4.5v to 26.5v c1 22pf c2 22pf intv cc v in pgood *stuff with a 0 resistor for 4.5v < v in < 5.5v
ltm4619 19 4619fa figure 19. typical 4.5v to 26.5v input, 1.2v and 1.5v outputs at 4a design with adjusted frequency at 500khz t ypical applica t ions 4619 f19 v in v fb1 comp1 v out1 tk/ss1 run1 pgood freq/pllfltr v fb2 comp2 v out2 tk/ss2 run2 intv cc mode/pllin ltm4619 sgnd pgnd 121k 100k 68.1k r2 1.21k c out2 100f 2 c out1 100f 2 v out2 1.5v/4a v out1 1.2v/4a 0.1f c in 10f 2 0.1f v in 4.5v to 26.5v c1 22pf c2 22pf r1 3.83k external 5v supply for input voltage below 5.5v intv cc pgood extv cc
ltm4619 20 4619fa t ypical applica t ions figure 20. output paralleled ltm4619 module for 5v output at 8a design 4619 f20 v in comp1 comp2 tk/ss1 tk/ss2 pgood freq/pllfltr v fb1 v fb2 v out1 v out2 run2 run1 intv cc extv cc mode/pllin ltm4619 sgnd pgnd r1 5.76k c4 100f c5 330f v out2 5v/8a c3 0.1f c in 10f v in 6v to 26.5v c1 51pf +
ltm4619 21 4619fa t ypical applica t ions figure 21. 4-phase, four outputs (5v, 3.3v, 2.5v and 1.8v) with tracking 4619 f21 v in v fb1 comp1 v out1 tk/ss1 run1 pgood freq/pllfltr v fb2 comp2 v out2 tk/ss2 run2 extv cc intv cc mode/pllin ltm4619 clock sync, 0 phase clock sync, 90 phase sgnd pgnd r3 11.5k c4 22f c5 220f v out2 3.3v/4a c1 0.1f r4 19.1k c10 22pf c11 22pf r1 60.4k r2 19.1k v out1 + c3 22f c2 220f v out1 5v/4a + v in v fb1 comp1 v out1 tk/ss1 run1 pgood freq/pllfltr v fb2 comp2 v out2 tk/ss2 run2 extv cc intv cc mode/pllin ltm4619 sgnd pgnd r7 28k c6 22f c7 220f v out4 1.8v/4a r8 48.7k c12 22pf c13 22pf r5 60.4k r6 48.7k v out1 r10 60.4k r11 28k v out1 + c8 22f c9 220f v out3 2.5v/4a + c in2 10f 2x c in1 330f v in 6v to 26.5v + v + gnd set out1 out2 mod ltc6908-2 c3 0.1f r9 143k on/off 2 phase oscillator
ltm4619 22 4619fa pin assignment table 4 (arranged by pin function) pin name pin name pin name pin name a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 v out2 v out2 v out2 gnd gnd gnd gnd gnd gnd v out1 v out1 v out1 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 v out2 v out2 v out2 gnd gnd gnd gnd gnd gnd v out1 v out1 v out1 g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 g11 g12 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd k1 k2 k3 k4 k5 k6 k7 k8 k9 k10 k11 k12 v in v in v in v in tk2 v fb2 v fb1 tk1 v in v in v in v in b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 v out2 v out2 v out2 gnd gnd gnd gnd gnd gnd v out1 v out1 v out1 e1 e2 e3 e4 e5 e6 e7 e8 e9 e10 e11 e12 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 gnd gnd sw2 gnd pgood sgnd sgnd mode/pllin gnd sw1 gnd gnd l1 l2 l3 l4 l5 l6 l7 l8 l9 l10 l11 l12 v in v in v in v in v in comp2 comp1 v in v in v in v in v in c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 v out2 v out2 v out2 gnd gnd gnd gnd gnd gnd v out1 v out1 v out1 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 gnd gnd gnd gnd gnd intv cc gnd gnd gnd gnd gnd gnd j1 j2 j3 j4 j5 j6 j7 j8 j9 j10 j11 j12 v in v in v in extv cc run2 sgnd sgnd freq/pllfltr run1 v in v in v in m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 v in v in v in v in v in v in v in v in v in v in v in v in p ackage descrip t ion
ltm4619 23 4619fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion lga package 144-lead (15mm 15mm 2.82mm) (reference ltc dwg # 05-08-1816) notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters land designation per jesd mo-222, spp-010 5. primary datum -z- is seating plane 6. the total number of pads: 144 4 3 details of pad #1 identifier are optional, but must be located within the zone indicated. the pad #1 identifier may be either a mold or marked feature symbol aaa bbb eee tolerance 0.10 0.10 0.05 2.72 ? 2.92 detail b detail b substrate mold cap 0.27 ? 0.37 2.45 ? 2.55 bbb z z 15 bsc package top view 15 bsc 4 pad 1 corner x y aaa z aaa z detail a 13.97 bsc 1.27 bsc 13.97 bsc 0.12 ? 0.28 package bottom view 3 pads see notes suggested pcb layout top view 0.0000 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 0.0000 6.9850 lga 144 0308 rev a ltmxxxxxx mmodule tray pin 1 bevel package in tray loading orientation component pin ?a1? dia 0.630 pad 1 3x, c (0.22 x45) detail a 0.630 0.025 sq. 143x s yxeee l k j h g f e d c b m a 12345678 10 9 1112
ltm4619 24 4619fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2009 lt 0111 rev a ? printed in usa r ela t e d p ar t s p ackage p ho t ograph part number description comments ltm4614 dual, 4a, low v in , dc/dc module regulator 2.375v v in 5.5v, 0.8v v out 5v, 15mm w 15mm w 2.8mm lga ltm4615 triple, low v in , dc/dc module regulator two 4a outputs and one 1.5a, 15mm w 15mm w 2.8mm lga ltm4616 dual, 8a, low v in , dc/dc module regulator 2.7v v in 5.5v, 0.6v v out 5v, 15mm w 15mm w 2.8mm lga ltm4628 dual, 8a, 26v, dc/dc module regulator 4.5v v in 28.5v, 0.6v v out 5.5v, remote sense amplifier, internal temperature sensing diode output, 15mm w 15mm w 4.3mm lga

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